- All Products
- Software Integrity
- Semiconductor IP
- Verification
- Design
- Silicon Engineering
- Application Security Services
- Dynamic Analysis (DAST)
- Mobile Application Security
- Penetration Testing
- Managed Static Analysis
- All Services
- Software Security
- Silicon Design
- Community
- About Us
< All Products
< All Products
< All Products
< All Products
< All Products
< All Products
< overview
All Products
+ Software Integrity + Semiconductor IP + Verification + Design + Silicon Engineering + Optical Solutions< Software Integrity
< Software Integrity
Application Security Services
Dynamic Analysis (DAST) Mobile Application Security Penetration Testing Managed Static Analysis< Software Integrity
< Software Integrity
< Software Integrity
Blog
< Software Integrity
Support
< overview
Software Integrity
+ Application Security Products + Application Security Services + Resources + Training & Education Blog Support< Semiconductor IP
< Semiconductor IP
Memories & Libraries
Logic Libraries Memory Compliers Duet Packages HPC Design Kit Embedded Test & Repair Non-Volatile Memory< Semiconductor IP
< Semiconductor IP
Processor Solutions
ARC Processors Embedded Vision Processors Development Tools Operating Systems Ecosystems ASIP Tools< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< overview
< Verification
< Verification
< Verification
< Design
< Design
< Design
< overview
< Silicon Engineering
< overview
< main menu
< Solutions
< Solutions
Industry Solutions
Automotive Cloud Computing Financial Services Industrial Controls Systems Healthcare< Solutions
< overview
< All Services
< All Services
< All Services
< overview
< Software Security
< Software Security
Managed Services
< Software Security
Program Development & Design
Maturity Model (BSIMM) Maturity Action Plan (MAP) Policies & Standards Security Metrics Software Security-in-a-Box< Software Security
< Software Security
Support
< overview
Software Security
+ Software Security Services Managed Services + Program Development & Design + Training Support< Silicon Design
< Silicon Design
< Silicon Design
< Silicon Design
< main menu
< Community
< Community
< Community
< Community
Interoperability
ARC Access HAPS Connect HSPICE Integrator In-Sync System-Level Catalyst TAP-in VC Apps Access< Community
< Community
< Community
< overview
Community
+ Community + SNUG + Partners + Interoperability + Academic Programs + Company Blogs + BSIMM< About Us
< About Us
< About Us
< About Us
< About Us
DesignWare ARC Data Fusion IP Subsystem
IoT applications increasingly require advanced sensing capabilities that extend beyond what traditional sensors provide. Functions such as face detection, voice and gesture recognition require an efficient combination of RISC and DSP processing. The DesignWare® ARC® Data Fusion IP Subsystem is a complete, pre-verified, hardware and software solution optimized for a wide range of ultra-low power IoT applications. It is designed for fast and easy integration within a larger system context.
The fully configurable ARC Data Fusion IP Subsystem includes the choice of a low gate count and energy-efficient DesignWare ARC EM5D, EM7D, EM9D or EM11D processor for both RISC and DSP processing, accompanied by an extensive collection of I/O functions and fast math (trigonometric) accelerators. The software libraries of the subsystem contain small-footprint drivers for all I/O, plus DSP functions supporting signal processing. It also includes an audio processing software library of common functions, including gain control, mixer and sample rate converter. Tightly coupled PDM and I2S peripherals simplify integration of external audio devices and the hardware PDM interface implementation is 6X more energy efficient than the equivalent software implementation, with minimal gate count impact. The audio library and peripherals (PDM, I2S) are part of a voice/speech licensable option. An optional MIPI I3C master/slave peripheral, compliant with the MIPI Camera Control Interface (CCI), I2C and I3C specifications, provides a high-performance sensor interface. The integrated solution is optimized for “always on” data fusion combining sensor, voice, gesture and audio processing typically implemented in IoT edge devices.
Watch the Webinar to learn techniques to accelerate data fusion in your SoC.
Figure 1: DesignWare ARC Data Fusion IP Subsystem integrated hardware and software solution
DesignWare ARC Data Fusion IP Subsystem
| This demonstration shows always-on functions including 9D sensor fusion and voice activation, gesture recognition and face detection to control MP3 playback. The demo platform includes a silicon-based MCU with an integrated ARC EM5D-based Smart Data Fusion Subsystem and 2 megabytes of MONOS embedded flash. Rich Collins |
Highlights
Products
Downloads and Documentation
- Integrated, pre-verified hardware and software IP subsystem
- ARC EM processors with cache and DSP extensions deliver extremely low gate count and highly efficient processing performance
- Extensive library of software DSP functions enable sensor signal processing
- Hardware accelerators boost performance efficiency and reduce power consumption
- Integrated peripherals provide a wide range of SoC connectivity options for SoC/MCUs
- Options supporting higher performance voice/speech and sensor requirements
| Description: | Smart Data Fusion IP Subsystem |
| Name: | dwc_data_fusion_subsystem |
| Version: | 1.10a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Databooks Smart Data Fusion IP Subsystem DSP Databook Smart Data Fusion IP Subsystem I/O Databook Smart Data Fusion IP Subsystem Infrastructure Databook Smart Data Fusion IP Subsystem Voice DatabookQuickStart Smart Data Fusion IP Subsystem Starter KitRelease Notes Smart Data Fusion IP Subsystem Release NotesUser Manual Smart Data Fusion IP Subsystem User Guide |
| Download: | arc_datafusion_subsystem |
| Product Code: | B014-0 |