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DesignWare ARC Data Fusion IP Subsystem
IoT applications increasingly require advanced sensing capabilities that extend beyond what traditional sensors provide. Functions such as face detection, voice and gesture recognition require an efficient combination of RISC and DSP processing. The DesignWare® ARC® Data Fusion IP Subsystem is a complete, pre-verified, hardware and software solution optimized for a wide range of ultra-low power IoT applications. It is designed for fast and easy integration within a larger system context.
The fully configurable ARC Data Fusion IP Subsystem includes the choice of a low gate count and energy-efficient DesignWare ARC EM5D, EM7D, EM9D or EM11D processor for both RISC and DSP processing, accompanied by an extensive collection of I/O functions and fast math (trigonometric) accelerators. The software libraries of the subsystem contain small-footprint drivers for all I/O, plus DSP functions supporting signal processing. It also includes an audio processing software library of common functions, including gain control, mixer and sample rate converter. Tightly coupled PDM and I2S peripherals simplify integration of external audio devices and the hardware PDM interface implementation is 6X more energy efficient than the equivalent software implementation, with minimal gate count impact. The audio library and peripherals (PDM, I2S) are part of a voice/speech licensable option. The integrated solution is optimized for “always on” data fusion combining sensor, voice, gesture and audio processing typically implemented in IoT edge devices.
Watch the Webinar to learn techniques to accelerate data fusion in your SoC.
Figure 1: DesignWare ARC Data Fusion IP Subsystem integrated hardware and software solution
DesignWare ARC Data Fusion IP Subsystem
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| This demonstration shows always-on functions including 9D sensor fusion and voice activation, gesture recognition and face detection to control MP3 playback. The demo platform includes a silicon-based MCU with an integrated ARC EM5D-based Smart Data Fusion Subsystem and 2 megabytes of MONOS embedded flash. Rich Collins |
- Integrated, pre-verified hardware and software IP subsystem
- ARC EM processors with cache and DSP extensions deliver extremely low gate count and highly efficient processing performance
- Extensive library of software DSP functions enable sensor signal processing
- Hardware accelerators boost performance efficiency and reduce power consumption
- Integrated peripherals provide a wide range of SoC connectivity options for SoC/MCUs
- Options supporting higher performance voice/speech and sensor requirements