Complex system-on-chip (SoC) requirements can include security at various application layers. The Synopsys Security Protocol Accelerator SMx (SPAcc-SMx) IP addresses the application space requiring the use of Chinese security algorithms SM3 and SM4.
The SPAcc IP offers high throughput with support for mixed packet size traffic and low latency to preserve quality of service in voice and video applications in single- and multi-core processor architectures. The product is highly customer configurable enabling solutions to be tuned for specific applications providing differentiation in the market.
Most security protocols require computationally intensive confidentiality (e.g., SM4) and authentication (e.g., SM3) algorithms to be applied to the data. The Synopsys SPAcc-SMx IP provides a framework to apply the algorithms that include a programmable sequencer, secure DMA engine, and cryptographic/hashing resources that can handle a variety of protocols.
The SPAcc-SMx product reduces the system bus traffic and increases throughput by supporting efficient data sequencing as well as parallel processing of cryptographic operations (authentication and encryption/decryption).
Synopsys Security Protocol Accelerator for SM3 and SM4 Cryptographic Algorithms Datasheet
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- Highly customer configurable, silicon-proven security accelerator
- Support for Chinese security SM3 and SM4 (modes: ECB, CTR, CBC, CCM, GCM, XTS) algorithms
- Option: Differential Power Analysis (DPA) countermeasures for SM4
- Built-in scatter/gather DMA capability offloads the host processor
- Secure Key Port to access confidential data stored in NVM
- Optimal bus utilization
- Increased throughput with combined hash and cipher operations
- Secure bus option for systems which differentiate between secure and normal processing modes
- Virtualization – allows sharing between multiple CPUs
- QoS capability allows multiple command priority queues for enhanced traffic management capabilities
- IV import feature – permits DMA of IV with associated payload
- Reduced system processor loading with programmable interrupt coalescence
- Dual-clock domain capability to run interface and crypto content in different clock domains
- Support for big- or little-endian
- Selectable 32- or 64-bit bus interfaces
- AMBA AXI4
- AMBA AHB