As the amount of software in embedded processor applications increases, system developers are looking for new ways to store boot code and other software. Traditionally, many systems stored code in an external memory, often Flash or EEPROM, and downloaded it to the processor chip as needed. Due to the slow access times associated with external Flash memory, the code was downloaded to embedded SRAM on the processor chip.
The power required to access off-chip memory, along with security concerns of storing valuable code in external memory, has driven designers to store code in OTP on the processor chip. The memory technology used for this storage must be high density, low cost, low power, and very secure and reliable. To reduce chip production cost, embedded OTP technology should provide an easy path for converting programmable OTP into mask ROM when code is frozen.
Synopsys XHC OTP NVM addresses these requirements with a high-capacity, highly secure anti-fuse bit cell architecture in densities up to 1Mb. The field-programmable OTP NVM is virtually impossible to reverse engineer to ensure integrity and prevent the theft of valuable code. It runs in standard logic CMOS processes with no added masks or process steps, adding zero cost to the process flow.
Synopsys XBC/XHC OTP NVM IP - SLP Architecture
Synopsys XBC/XHC OTP NVM IP – SLP_A Architecture
Synopsys XBC/XHC OTP NVM IP – SLP_B Architecture
Synopsys XHC OTP NVM IP – SLP_C Architecture
Synopsys XHC/XBC OTP NVM IP - SHF Architecture
- Cost-effective solution in standard CMOS process requires no additional masks
- Available in CMOS RF, SOI, and Mixed Mode processes
- Highly secure anti-fuse bit cell
- Wide I/O supply voltage range
- Fast access time, external or field programming
- Optimized for area and low standby power
- Qualified for consumer and automotive applications