Synopsys Multi-Port Memory

Synopsys' four-port register file memory compilers and asynchronous register file memory compilers address the requirements of designers in the networking and communications markets.

The four-port register file memory compilers have two write ports and two read ports, providing parallel memory access most suitable for compute-intensive applications that require extreme bandwidth capabilities. The high-speed pseudo four-port and pseudo quad-port SRAM architectures in 7nm support parallel operations with significant area reduction. The P4P and PQP allows up to two and four simultaneous read or write operations respectively.

The asynchronous register file memories have one synchronous write port and one asynchronous read port.


  • Multi-port memory features
    • Up to four independent read ports and two independent write ports
    • Supports parallel operations to increase system bandwidth
    • Zero clock latency overhead
    • Deterministic timing
    • Easily integrates on chip with existing design flows
    • High bandwidth with the best density and power savings for critical applications requiring multi-port architectures
  • Asynchronous register file features
    • Independent write port and independent asynchronous read port
    • Enables fast access times for downstream operation