2022-10-17 10:11:00
Synopsys USB 3.2 PHY IP provides designers with the industry's best combination of low area and low power with support for the leading process technologies such as 7nm FinFET. The USB 3.2 PHYs use a single efficient GDSII design that SuperSpeed USB 3.2 Gen 1 at 5Gbps, USB 3.2 Gen2 at 10Gbps, and USB 3.2 Gen2 x2 at 20Gbps.
Synopsys USB IP is the most certified USB IP solution in the industry. With experience supporting over 3,500 design wins and approximately three billion silicon-proven units shipped, Synopsys' USB 3.2 IP solution, consisting of a controller, PHYs, verification IP, and IP subsystems, enables designers to lower integration risk and speed time-to-market.
Synopsys SuperSpeed USB 3.2 IP Solution
Highlights
Products
Downloads and Documentation
- Synopsys USB 3.2 PHYs and controllers offer high-performance throughput
- USB-C 3.2 PHY IP supports USB Type-C specification
- Supports SuperSpeed USB 3.2 Gen1 at 5Gbps, USB 3.2 Gen2 at 10Gbps, and USB 3.2 Gen2 x2 at 20Gbps
- Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
- Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
- Supports Hi-Speed 480 Mbps and Full Speed 12 Mbps
| USB-C 3.2 DP/TX PHY for GF 12LP+, North/South poly orientation | STARs |
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| USB-C 3.2 DP/TX PHY ebdaux for SS SF4E, North/South poly orientation | STARs |
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| USB-C 3.2 DP/TX PHY ebdaux for TSMC N5, North/South poly orientation | STARs |
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| USB-C 3.2 SS/SSP PHY, Type-C - SS SF4E, North/South Poly Orientation | STARs |
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| USB-C 3.2 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation | STARs |
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| USB-C 3.2 SS/SSP PHY, Type-C - TSMC 6FF, North/South Poly Orientation | STARs |
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| USB-C 3.2 SS/SSP PHY, Type-C - TSMC 7FF, North/South Poly Orientation | STARs |
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| Description: |
USB-C 3.2 DP/TX PHY ebdaux for SS SF4E, North/South poly orientation |
| Name: |
dwc_usbc32dptx_ebdaux_phy_ss4lpens |
| Version: |
3.08a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes C10 Hardware Emulation Application Note ( PDF | HTML )
DesignWare Cores Consumer 10G Type-C USB 3.2 DP ATE Test Bench (Doc Version: 3.07a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare Cores Type-C USB3.2SSP+ / DP Alt PHY for SS4LPE (PHY Version: 3.08a) ( PDF | HTML )
Type-C USB3.2SSP+ / DP Alt PCS for the DesignWare Type-C USB3.2SSP+ / DP Alt PHY (PCS Version: 3.33a) ( PDF | HTML )
Type-C USB3.2SSP+ / DP Alt PCS for the DesignWare Type-C USB3.2SSP+ / DP Alt PHY (PCS Version: 3.53a) ( PDF | HTML )
Release Notes DWC USBC3.2 DP PHY x4 NS for SS 4LPE 1.2V Release Notes (PHY Version: 3.08a) ( TEXT )
|
| Download: |
dwc_usbc32dptx_ebdaux_phy_ss4lpens |
| Product Code: |
E992-0 |
| Description: |
USB-C 3.2 DP/TX PHY ebdaux for TSMC N5, North/South poly orientation |
| Name: |
dwc_usbc32dptx_ebdaux_phy_tsmc5ffns |
| Version: |
4.01c |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores Consumer 10G Type-C USB 3.2 DP ATE Test Bench (Doc Version: 3.07a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( HTML )
Synopsys PHY IP Consumer 10G Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare Cores Type-C USB3.2SSP+ / DP Alt PHY for TSMC5FF (PHY Version: 4.01c) ( PDF | HTML )
Type-C USB3.2SSP+ / DP Alt PCS for the DesignWare Cores Type-C USB3.2SSP+ / DP Alt PHY (PCS Version: 3.55a) ( PDF | HTML )
Reference Manual DesignWare Cores Type-C USB3.2SSP+ / DP Alt PHY for TSMC5FF Reference Manual (PHY Version: 4.01c) ( PDF | HTML )
Release Notes DWC USBC3.2 / DP for TSMC5FF 1.2V Release Notes (PHY Version 4.01c) ( TEXT )
|
| Download: |
dwc_usbc32dptx_ebdaux_phy_tsmc5ffns |
| Product Code: |
E508-0 |
| Description: |
USB-C 3.2 SS/SSP PHY, Type-C - SS SF4E, North/South Poly Orientation |
| Name: |
dwc_usbc32sspphy_ss4lpens |
| Version: |
3.07a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores Consumer 10 Type-C USB3.2SS+ PHY ATE Test Bench (ATE Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare Cores Type-C USB3.2SS+ PHY Databook for Samsung 4 LPE (PHY Version: 3.07a) ( PDF | HTML )
Type-C USB3.2SSP+ PCS for the DesignWare Cores Type-C USB3.2SSP+ PHY (PCS Version: 3.42a) ( PDF | HTML )
Release Notes DesignWare Cores USBC3.2 SSP PHY x2 NS for SS 4LPE 1.2V (PHY Version: 3.07a) ( TEXT )
|
| Download: |
dwc_usbc32sspphy_ss4lpens |
| Product Code: |
G828-0 |
| Description: |
USB-C 3.2 SS/SSP PHY, Type-C - TSMC 6FF, North/South Poly Orientation |
| Name: |
dwc_usbc32sspphy_tsmc6ffns |
| Version: |
4.03a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores USBC3.2SSP+ PHY ATE Test Bench for TSMC6FF (Doc Version: 1.10a) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare Cores USBC3.2SSP+ PHY for TSMC6FF (PHY Version: 4.03a) ( PDF | HTML )
Type-C USB3.2SSP+ PCS for the DesignWare Cores Type-C USB3.2SSP+ PHY (PCS Version: 3.54a) ( PDF | HTML )
Datasheet Synopsys SuperSpeed USB 3.2 IP Solution ( PDF )
Release Notes Type-C USB3.2SSP+ PHY NS for TSMC6FF 1.8V Release Notes (PHY Version: 4.03a) ( TEXT )
White Paper USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
|
| Download: |
dwc_usbc32sspphy_tsmc6ffns |
| Product Code: |
F928-0 |
| Description: |
USB-C 3.2 SS/SSP PHY, Type-C - TSMC 7FF, North/South Poly Orientation |
| Name: |
dwc_usbc32sspphy_tsmc7ffns |
| Version: |
4.03a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores Type-C USBC 3.2 SSP+ PHY ATE Test Bench (Doc Version: 1.10a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare Cores Type-C USB 3.2 SSP+ PHY for TSMC7FF (PHY Version: 4.03a) ( PDF | HTML )
Type-C USB3.2SSP+ PCS for the DesignWare Cores Type-C USB3.2SSP+ PHY (PCS Version: 3.54a) ( PDF | HTML )
Datasheet Synopsys SuperSpeed USB 3.2 IP Solution ( PDF )
Release Notes DesignWare Cores Type-C USBC 3.2 SSP+ PHY for TSMC7FF Release Notes (PHY Ver: 4.03a) ( TEXT )
White Paper USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
|
| Download: |
dwc_usbc32sspphy_tsmc7ffns |
| Product Code: |
D921-0 |
| Description: |
USB-C 3.2 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation |
| Name: |
dwc_usbc32sspphy_tsmc5ffns |
| Version: |
4.01c |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores USBC 3.2 SSP+ PHY ATE Test Bench (Doc Version: 1.30a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( HTML )
Synopsys PHY IP Consumer 10G Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare Cores Type-C USB 3.2 SSP+ PHY Databook for TSMC5FF (PHY Version: 4.01c) ( PDF | HTML )
Type-C USB3.2SSP+ PCS for the DesignWare Cores Type-C USB3.2SSP+ PHY (PCS Version: 3.55a) ( PDF | HTML )
Datasheet Synopsys SuperSpeed USB 3.2 IP Solution ( PDF )
Reference Manual DesignWare Cores Type-C USB 3.2 SSP+ PHY Reference Manual for TSMC5FF (PHY Version: 4.01c) ( PDF | HTML )
Release Notes DWC USBC3.2 SSP+ PHY NS for TSMC5FF 1.2V Release Notes (PHY Version: 4.01c) ( TEXT )
White Paper USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
|
| Download: |
dwc_usbc32sspphy_tsmc5ffns |
| Product Code: |
E507-0 |
