Synopsys' DesignWare USB 3.2 PHY IP provides designers with the industry's best combination of low area and low power with support for the leading process technologies such as 7nm FinFET. The USB 3.2 PHYs use a single efficient GDSII design that SuperSpeed USB 3.2 Gen 1 at 5Gbps, USB 3.2 Gen2 at 10Gbps, and USB 3.2 Gen2 x2 at 20Gbps.
Synopsys DesignWare USB IP is the most certified USB IP solution in the industry. With experience supporting over 3,500 design wins and approximately three billion silicon-proven units shipped, Synopsys' USB 3.2 IP solution, consisting of a controller, PHYs, verification IP, and IP subsystems, enables designers to lower integration risk and speed time-to-market.
DesignWare SuperSpeed USB 3.2 IP Solution
Downloads and Documentation
- DesignWare USB 3.2 PHYs and controllers offer high-performance throughput
- USB-C 3.2 PHY IP supports USB Type-C specification
- Supports SuperSpeed USB 3.2 Gen1 at 5Gbps, USB 3.2 Gen2 at 10Gbps, and USB 3.2 Gen2 x2 at 20Gbps
- Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
- Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
- Supports Hi-Speed 480 Mbps and Full Speed 12 Mbps
|USB-C 3.2 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation||STARs
|USB-C 3.2 SS/SSP PHY, Type-C - TSMC 6FF, North/South Poly Orientation||STARs
|USB-C 3.2 SS/SSP PHY, Type-C - TSMC 7FF, North/South Poly Orientation||STARs