The Synopsys USB 3.0 xHCI Host Controller is a set of synthesizable soft IP that ASIC/FPGA designers can use to implement a complete USB 3.0 Host for 5 Gbps speeds. The USB 3.0 Host Controller compliant with the specifications for SuperSpeed, High-Speed, Full-Speed, and Low-Speed USB speeds. Optimizing development time and minimizing engineering risk, the Synopsys USB 3.0 Host Controller helps designers bring their host and peripheral designs to market faster for wired and wireless applications such as smart phones, tablets, TVs, set-top boxes, cameras, modems, game consoles, PCs, and telecommunications equipment. In addition, the IP is silicon proven in design process nodes from 180-nm to 20-nm.
The Synopsys USB 3.0 Host Controller can be easily bridged to any industry-standard bus and includes both the AMBA™ AHB and AXI interfaces. The Host Controller can be used as an SSIC Controller with a MIPI M-PHY for low power mobile applications. It also has the HSIC feature to connect to HSIC PHYs.
Synopsys USB Controllers have shipped in over one billion units for electronics leading companies worldwide. Using Synopsys USB IP significantly reduces development time and engineering risk, bringing USB-based SoCs to market faster.
Synopsys USB IP is the most certified IP solution in the industry. With over 3,000 design wins, Synopsys' complete USB IP solution--consisting of controllers, PHYs, verification IP, drivers, and IP prototypes--enables designers to lower integration risk and speed time-to-market.
Synopsys SuperSpeed USB 3.0 Complete Solution
Downloads and Documentation
- Certified by the USB-IF
- SuperSpeed (5 Gbps), high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) capabilities
- Optimized power management with SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
- Configurable data buffering options to fine-tune performance/area trade-offs
- Host Controller compatible with common operating systems that support the xHCI standard, such as Windows 8 and Linux
- xHCI debug capability
- AXI and AHB interfaces or Native interface for bridging to other system buses
- Compatible with Synopsys' Certified USB 2.0 PHYs and USB 3.0 PHYs
- Verilog source code
- Verilog Test Bench included
|SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC