Synopsys Ternary Content-Addressable Memory Compilers

Synopsys embedded ternary content addressable memories (TCAMs) help networking designers meet the demand for wire-speed packet processing, access control lists and more for high-bandwidth delivery. Synopsys ternary CAM compilers are available in geometries from 7nm to 180nm across multiple foundries.

High-Performance, High-Density Embedded CAM Compilers for Network Applications

Synopsys offers a broad range of feature-rich, high-performance, high-density embedded TCAM compilers. Our ternary CAM compilers provide high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.

User-Selectable Features

In addition to a full set of standard features, Synopsys TCAM compilers provide a comprehensive set of user-selectable features that are chosen at compile time. Designers can choose exactly the features that they need for a specific application to optimize performance, power or area (PPA).

  • Partial pipelined search
  • Priority encoder
  • Redundancy

Synopsys CAM designs are available in 7nm to 180nm geometries across multiple foundries, optimized to meet challenging PPA requirements of IDM and leading foundry processes. We can supply ternary CAM instances or compilers to fit the number of instances required.

Synopsys Ternary CAM Compilers


  • Duo architecture for extreme area and power reduction
  • Multiple architectures available in 7nm, 10nm, 14nm, 16nm, 28nm, 40nm, 65nm, 90nm, 130nm and 180nm
  • Flexible selection of width and depth with up to 1K entries and 160Kb macro size
  • Easily cascadable to increase search depth without degradation in performance
  • Single-cycle search, read and write operations
  • Smart power management and partial-pipelined search option for reduced power
  • Fast cycle and access time: the 7nm TCAM offers more than a 50 percent increase in performance compared to previous FinFET generations
  • Valid-bit, global and local valid-bit reset
  • Match-in and match-out flag for each entry
  • Flexible masking (bit/group/global)
  • Optimized layout for high density and high performance