The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) cost, low-power consumption in consumer applications. The multi-protocol 6G PHY provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express, SATA, and Ethernet standards. The PHY incorporates advanced power saving features such as L1 substates power management in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode to further save active power.
The PHY's Automatic Test Equipment (ATE) capabilities and wirebond packaging reduce the overall BOM cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerate time-to-market.
DesignWare Multi-Protocol 6G PHY Datasheet
- Supports 1.25 to 6.25 Gbps data rates
- Supports PCI Express 2.1/1.1, SATA 6G/3G/1.5G, XAUI, SGMII, CEI-6G specifications
- Supports x1 to x16 macro configurations
- Superior signal integrity enabled by adaptive continuous time linear equalizer (CTLE), and feed forward equalization (FFE)
- Low active and standby power consumption compared to competing solutions due to L1 substates and novel transmitter design
- PCI Express Aggregation and bifurcation
- Spread Spectrum Clock (SSC)
- Embedded bit error rate (BER) tester and internal eye monitor
- Wirebond or flipchip packaging with flexible bumps
- Supports IEEE 1149.6 AC Boundary Scan
- Supports -40°C to 125°C Tj