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DesignWare Multi-Protocol 25G PHY
The multi-lane DesignWare® Multi-Protocol 25G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including PCI Express (PCIe) 4.0, 25G and 100G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), SATA and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 25G PHY delivers signal integrity and jitter performance that exceeds the standards’ electrical specifications.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The embedded bit error rate tester (BERT) and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayers (PCS) and digital controllers/Media Access Controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. Contact us now for more information and to discuss your 25G multi-protocol PHY IP needs.
DesignWare CCIX IP Complete Solution Datasheet DesignWare Multi-Protocol 25G PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
- Ethernet Electrical Energy Efficient (EEE)
- Reference clock sharing for aggregated macro configurations
- Continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
- Embedded bit error rate tester (BERT) and internal eye monitor
- Supports IEEE 1149.6 AC Boundary Scan
| 25G PHY, GF 14LPP x1 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, GF 14LPP x2 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, GF 14LPP x4 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, TSMC 12FFC x4 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, TSMC 12FFC x8 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, TSMC 16FFC x4 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, TSMC 16FFPGL x4 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, TSMC 7FF x2 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation | STARs | Subscribe |
| 25G PHY, TSMC 7nm | STARs | Subscribe |
| Description: | 25G PHY, GF 14LPP x1 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_gf14lpp_x1ns |
| Version: | 1.02a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Note DesignWare Cores Multi-Protocol 25G PHY ATE Test BenchComplete Solution Datasheet DesignWare CCIX IP Complete Solution DatasheetDatabooks DesignWare Cores Multi-Protocol 25G PHY for GF 14LPP Multi-Protocol 25G PCS for the DesignWare Cores Multi-Protocol 25G PHYRelease Notes  DesignWare Cores Multi-Protocol 25G PHY for GF 14LPP |
| Download: | E25-PHY_GF_14LPP_x1 |
| Product Code: | C666-0 |
| Description: | 25G PHY, GF 14LPP x2 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_gf14lpp_x2ns |
| Version: | 1.01a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | E25-PHY_GF_14LPP_x2 |
| Product Code: | D237-0 |
| Description: | 25G PHY, GF 14LPP x4 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_gf14lpp_x4ns |
| Version: | 1.02a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores Multi-Protocol 25G PHY ATE Test Bench DesignWare Cores SERDES PCB and Packaging Design GuideDatabooks DesignWare Cores Multi-Protocol 25G PHY for GF 14LPP Multi-Protocol 25G PCS for the DesignWare Cores Multi-Protocol 25G PHYRelease Notes DesignWare Cores Multi-Protocol 25G PHY for GF 14LPP |
| Download: | E25-PHY_GF_14LPP_x4 |
| Product Code: | D238-0 |
| Description: | 25G PHY, TSMC 12FFC x4 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_tsmc12ffc_x4ns |
| Version: | 1.02a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | E25-PHY_TSMC_12FFC_x4 |
| Product Code: | D110-0 |
| Description: | 25G PHY, TSMC 12FFC x8 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_tsmc12ffc_x8ns |
| Version: | 1.01a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | E25-PHY_TSMC_12FFC_x8 |
| Product Code: | D111-0 |
| Description: | 25G PHY, TSMC 16FFC x4 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_tsmc16ffc_x4ns |
| Version: | 1.02a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores Multi-Protocol 25G PHY ATE Test Bench DesignWare Cores SERDES PCB and Packaging Design GuideComplete Solution Datasheets DesignWare CCIX IP Complete Solution Datasheet DesignWare IP for PCI Express Complete Solution DatasheetDatabooks DesignWare Cores Multi-Protocol 25G PHY for TSMC 16FFC Multi-Protocol 25G PCS for the DesignWare Cores Multi-Protocol 25G PHYRelease Notes DesignWare Cores Multi-Protocol 25G PHY for TSMC 16FFC |
| Download: | E25-PHY_TSMC_16FFC_x4 |
| Product Code: | C419-0 |
| Description: | 25G PHY, TSMC 16FFPGL x4 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_tsmc16ffpgl_x4ns |
| Version: | 1.02a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | E25-PHY_TSMC_16FFPGL_x4 |
| Product Code: | D239-0 |
| Description: | 25G PHY, TSMC 7FF x2 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_tsmc7ff_x2ns |
| Version: | 1.07a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | E25-PHY_TSMC_N7_x2 |
| Product Code: | D230-0 |
| Description: | 25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation |
| Name: | dwc_25g_phy_tsmc7ff_x4ns |
| Version: | 1.06a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | E25-PHY_TSMC_N7_x4 |
| Product Code: | D293-0 |
| Description: | 25G PHY, TSMC 7nm |
| Name: | dwc_25g_phy_tsmc7nm |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Product Code: |