2022-10-14 12:21:40
The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including PCI Express (PCIe) 4.0, 25G and 100G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), SATA and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 25G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The embedded bit error rate tester (BERT) and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Coding Sublayers (PCS) and digital controllers/Media Access Controllers (MACs) to reduce design time and to help designers achieve
first-pass silicon success.
Contact us now for more information and to discuss your 25G multi-protocol PHY IP needs.
Synopsys CCIX IP Complete Solution Datasheet
Synopsys Multi-Protocol 25G PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
- Ethernet Electrical Energy Efficient (EEE)
- Reference clock sharing for aggregated macro configurations
- Continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
- Embedded bit error rate tester (BERT) and internal eye monitor
- Supports IEEE 1149.6 AC Boundary Scan
| 25G MR Ethernet PHY, GF 14LPP x1 North/South (vertical) poly orientation | STARs |
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| 25G MR Ethernet PHY, GF 14LPP x2 North/South (vertical) poly orientation | STARs |
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| 25G MR Ethernet PHY, GF 14LPP x4 North/South (vertical) poly orientation | STARs |
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| 25G MR Ethernet PHY, TSMC 12FFC x4 North/South (vertical) poly orientation | STARs |
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| 25G MR Ethernet PHY, TSMC 12FFC x8 North/South (vertical) poly orientation | STARs |
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| 25G MR Ethernet PHY, TSMC 16FFC x1 North/South (vertical) poly orientation | STARs |
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| 25G MR Ethernet PHY, TSMC 16FFC x4 North/South (vertical) poly orientation | STARs |
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| 25G MR Ethernet PHY, TSMC 7FF x2 North/South (vertical) poly orientation | STARs |
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| 25G MR Ethernet PHY, TSMC 7FF x4 North/South (vertical) poly orientation | STARs |
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| 25G PHY, GF 12LP x1 North/South (vertical) poly orientation | STARs |
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| 25G PHY, GF 12LP x2 North/South (vertical) poly orientation | STARs |
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| 25G PHY, GF 12LP x4 North/South (vertical) poly orientation | STARs |
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| 25G PHY, GF 14LPP x1 North/South (vertical) poly orientation | STARs |
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| 25G PHY, GF 14LPP x2 North/South (vertical) poly orientation | STARs |
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| 25G PHY, GF 14LPP x4 North/South (vertical) poly orientation | STARs |
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| 25G PHY, GF 14LPP x8 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC 12FFC x4 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC 12FFC x8 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC 16FFC x1 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC 16FFC x4 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC 16FFPGL x4 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC N6 x2 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC 7FF x1 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC 7FF x2 North/South (vertical) poly orientation | STARs |
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| 25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation | STARs |
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| Description: |
25G MR Ethernet PHY, TSMC 16FFC x1 North/South (vertical) poly orientation |
| Name: |
dwc_25g_ethernet_phy_tsmc16ffc_x1ns |
| Version: |
1.03a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
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| Product Type: |
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Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G One-Lane Ethernet PHY for TSMC 16FFC Databook (PHY Version: 1.03a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 25G One-Lane PHY for TSMC 16FFC Databook (PHY Version: 1.03a) ( HTML )
DesignWare® Cores Multi-Protocol 25G One-Lane PHY for TSMC 16FFC Databook (PHY Version: 1.03b) ( PDF | HTML )
|
| Download: |
25G-M-ENET-PHY_TSMC_16FFC_x1 |
| Product Code: |
D969-0 |
| Description: |
25G PHY, GF 12LP x1 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_gf12lp_x1ns |
| Version: |
1.01a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
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| Product Type: |
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Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 1.1) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G PHY for GF 12LP Databook x1 (PHY Version: 1.01a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (PCS Version: 1.41, July 24, 2020) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 25G PHY for GF 12LP x1 Release Notes (PHY Version: 1.01a) ( TEXT )
|
| Download: |
dwc_25g_phy_gf12lp_x1ns |
| Product Code: |
E398-0 |
| Description: |
25G PHY, GF 12LP x2 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_gf12lp_x2ns |
| Version: |
1.01a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
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| Product Type: |
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Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 1.1) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G PHY for GF 12LP Databook x2 (PHY Version: 1.01a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (PCS Version: 1.41, July 24, 2020) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 25G PHY for GF 12LP x2 Release Notes (PHY Version: 1.01a) ( TEXT )
|
| Download: |
dwc_25g_phy_gf12lp_x2ns |
| Product Code: |
E399-0 |
| Description: |
25G PHY, GF 12LP x4 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_gf12lp_x4ns |
| Version: |
1.01a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 1.1) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for GF 12LP Databook (PHY Version: 1.00a) ( PDF )
DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for GF 12LP Databook (PHY Version: 1.01a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (PCS Version: 1.41, July 24, 2020) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 25G PHY for GF 12LP Release Notes (PHY Version: 1.00a) ( TEXT )
DesignWare® Cores Multi-Protocol 25G PHY for GF 12LP Release Notes (PHY Version: 1.01a) ( TEXT )
|
| Download: |
dwc_25g_phy_gf12lp_x4ns |
| Product Code: |
E400-0 |
| Description: |
25G PHY, GF 14LPP x1 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_gf14lpp_x1ns |
| Version: |
1.03c |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
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| Product Type: |
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Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.40) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G One-Lane PHY for GF 14LPP Databook (PHY Version: 1.03c) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (Doc Date: January 29, 2018) ( PDF | HTML )
Datasheet Synopsys CCIX IP Complete Solution Datasheet ( PDF )
Release Notes DesignWare® Cores Multi-Protocol 25G One-Lane PHY for GF 14LPP Release Notes (PHY Version: 1.03c) ( TEXT )
|
| Download: |
E25-PHY_GF_14LPP_x1 |
| Product Code: |
C666-0 |
| Description: |
25G PHY, GF 14LPP x2 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_gf14lpp_x2ns |
| Version: |
1.01a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
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Hide Documents...
Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G Two-Lane PHY for GF 14LPP Databook (PHY Version: 1.01a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (Doc Date: January 29, 2018) ( PDF | HTML )
|
| Download: |
E25-PHY_GF_14LPP_x2 |
| Product Code: |
D237-0 |
| Description: |
25G PHY, GF 14LPP x4 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_gf14lpp_x4ns |
| Version: |
1.04a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
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| Product Type: |
DesignWare Cores |
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Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.30) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for GF 14LPP Databook (PHY Version: 1.04a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (PCS Version: 1.40) ( PDF )
Release Notes DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for GF 14LPP Release Notes (PHY Version: 1.04a) ( TEXT )
|
| Download: |
E25-PHY_GF_14LPP_x4 |
| Product Code: |
D238-0 |
| Description: |
25G PHY, TSMC 12FFC x4 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc12ffc_x4ns |
| Version: |
1.04a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Synopsys PHY IP Multi-Protocol 25G PHY ATE Testbench Application Note (PHY Version: 0.50a_d1) ( PDF | HTML )
Databooks Multi-Protocol 25G PCS for the Synopsys PHY IP Multi-Protocol 25G PHY (PCS Version: 1.58a) ( PDF | HTML )
Synopsys PHY IP Multi-Protocol 25G PHY x4 for TSMC 12FFC Databook (PHY Version: 1.04a) ( PDF | HTML )
Release Notes Synopsys PHY IP Multi-Protocol 25G Four-Lane PHY for TSMC 12FFC Release Notes (PHY Version: 1.04a) ( TEXT )
|
| Download: |
dwc_25g_phy_tsmc12ffc_x4ns |
| Product Code: |
D110-0 |
| Description: |
25G PHY, TSMC 12FFC x8 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc12ffc_x8ns |
| Version: |
1.01a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.30) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G Eight-Lane PHY for TSMC 12FFC Databook (PHY Version: 1.01a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (Doc Date: January 29, 2018) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 25G Eight-Lane PHY for TSMC 12FFC Release Notes (PHY Version: 1.01a) ( TEXT )
|
| Download: |
E25-PHY_TSMC_12FFC_x8 |
| Product Code: |
D111-0 |
| Description: |
25G PHY, TSMC 16FFC x1 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc16ffc_x1ns |
| Version: |
1.03b |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.40a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G One-Lane Ethernet PHY for TSMC 16FFC Databook (PHY Version: 1.03a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 25G One-Lane PHY for TSMC 16FFC Databook (PHY Version: 1.03a) ( HTML )
DesignWare® Cores Multi-Protocol 25G One-Lane PHY for TSMC 16FFC Databook (PHY Version: 1.03b) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (PCS Version: 1.40) ( PDF )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY x1 (PCS Version: 1.54a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 25G One-Lane PHY for TSMC 16FFC Release Notes (PHY Version: 1.03a) ( TEXT )
DesignWare® Cores Multi-Protocol 25G One-Lane PHY for TSMC 16FFC Release Notes (PHY Version: 1.03b) ( TEXT )
|
| Download: |
dwc_25g_phy_tsmc16ffc_x1ns |
| Product Code: |
C725-0 |
| Description: |
25G PHY, TSMC 16FFC x4 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc16ffc_x4ns |
| Version: |
1.03a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.40a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G Four-Lane Ethernet PHY for TSMC 16FFC Databook (PHY Version: 1.03a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for TSMC 16FFC Databook (PHY Version: 1.03a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (PCS Version: 1.40) ( PDF )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY x1 (PCS Version: 1.54a) ( PDF | HTML )
Datasheets Synopsys CCIX IP Complete Solution Datasheet ( PDF )
Synopsys IP for PCI Express Complete Solution Datasheet ( PDF )
Release Notes DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for TSMC 16FFC Release Notes (PHY Version: 1.03a) ( TEXT )
|
| Download: |
E25-PHY_TSMC_16FFC_x4 |
| Product Code: |
C419-0 |
| Description: |
25G PHY, TSMC 16FFPGL x4 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc16ffpgl_x4ns |
| Version: |
1.02a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.30) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for TSMC 16FFPGL Databook (PHY Version: 1.02a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (Doc Date: January 29, 2018) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for TSMC 16FFC Release Notes (PHY Version: 1.02a) ( TEXT )
|
| Download: |
E25-PHY_TSMC_16FFPGL_x4 |
| Product Code: |
D239-0 |
| Description: |
25G PHY, TSMC 7FF x1 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc7ff_x1ns |
| Version: |
1.13a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.30a) ( HTML )
DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.60a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G PHY for TSMC 7FF Databook x1 (PHY Version: 1.13a_d1) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY x1 (Doc Version: 1.51b ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 25G One-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.02a) ( TEXT )
DesignWare® Cores Multi-Protocol 25G One-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.13a) ( TEXT )
|
| Download: |
dwc_25g_phy_tsmc7ff_x1ns |
| Product Code: |
E410-0 |
| Description: |
25G PHY, TSMC 7FF x2 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc7ff_x2ns |
| Version: |
1.09b |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.60a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 1.0) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G Two-Lane PHY for TSMC 7FF Databook (PHY Version: 1.09b) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY (PCS Version: 1.34) ( PDF )
Release Notes DesignWare® Cores Multi-Protocol 25G Two-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.09b) ( TEXT )
|
| Download: |
E25-PHY_TSMC_N7_x2 |
| Product Code: |
D230-0 |
| Description: |
25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc7ff_x4ns |
| Version: |
1.14a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
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Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench (Doc Version: 0.60a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Synopsys PHY IP 25G PHY Hardware Emulation Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF | HTML )
Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G PHY for TSMC 7FF Databook x4 (PHY Version: 1.14a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 25G PHY x4 for TSMC 7FF Reference Manual (PHY Version: 1.14a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY x4 (Doc Version: 1.56a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.13a) ( TEXT )
DesignWare® Cores Multi-Protocol 25G Four-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.14a) ( TEXT )
|
| Download: |
dwc_25g_phy_tsmc7ff_x4ns |
| Product Code: |
D293-0 |
| Description: |
25G PHY, TSMC N6 x2 North/South (vertical) poly orientation |
| Name: |
dwc_25g_phy_tsmc6ff_x2ns |
| Version: |
1.02a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores Multi-Protocol 25G PHY ATE Test Bench TSMC6FF (Doc Version: 0.30a) ( PDF )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databooks DesignWare® Cores Multi-Protocol 25G PHY x2 for TSMC 6FF Databook (PHY Version: 1.02a) ( PDF | HTML )
Multi-Protocol 25G PCS for the DesignWare® Cores Multi-Protocol 25G PHY TSMC6FF (Doc Version: 1.51b ( PDF )
Release Notes DesignWare® Cores Multi-Protocol 25G PHY x2 for TSMC 6FF Release Notes (PHY Version: 1.02a) ( TEXT )
|
| Download: |
dwc_25g_phy_tsmc6ff_x2ns |
| Product Code: |
F568-0 |
