DesignWare Multi-Protocol 25G PHY

The multi-lane DesignWare® Multi-Protocol 25G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 25G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards’ electrical specifications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including 25G and 100G Ethernet, PCI Express 4.0, and other industry-standard interconnect protocols.

The configurable transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage, frequency and temperature variations. The PHY provides advanced power management features for both standby and active power. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerate time-to-market.

Contact us now for more information and to discuss your 25G multi-protocol PHY IP needs.

DesignWare Multi-Protocol 25G PHY IP Datasheet


  • Supports1.25 to 25.8 Gbps data-rate
  • Supports PCI Express, Ethernet, and other industry standards
  • Supports x1 to x16 macro configurations with aggregation and bifurcation
  • Spread Spectrum Clock (SSC)
  • PCI Express Separate Refclk Independent SSC (SRIS)
  • PCI Express power management features
  • Ethernet Electrical Energy Efficient (EEE)
  • Reference clock sharing for aggregated macro configurations
  • Superior signal integrity across lossy channels enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
  • Embedded bit error rate (BER) tester and internal eye monitor
  • Supports IEEE 1149.6 AC Boundary Scan
  • Supports -40°C to 125°C Tj