DesignWare Universal DDR Memory Controller (uMCTL)

The Universal DDR Memory Controller (uMCTL) is a multi-port memory controller which accepts memory access requests from up to 32 application-side host ports. Application-side interfaces can be connected to the uMCTL either through the standard AMBA AXI/AHB bus interfaces or via Synopsys custom-defined extended native interface (ENIF). The configuration registers for the uMCTL are programmed via the AMBA 2.0 APB software interface.

The uMCTL connects to DDR PHYs via a DFI 2.1 interface to create a complete memory interface and control solution. The controller includes software configuration registers, which are accessed through an AMBA 2.0 APB interface.

DesignWare Universal DDR Memory and Protocol Controllers Datasheet


  • For new designs or for designs with higher speed requirements and greater RAS features, consider Synopsys’s Enhanced Universal DDR Memory Controller (uMCTL2)
  • Select a complete multi-ported enhanced Universal DDR Memory Controller offering up to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Memory Controller or Universal Protocol Controller
  • Support for JEDEC standard DDR2, DDR3, LPDDR/Mobile DDR, LPDDR2 and LPDDR3 SDRAMs
  • Compatible with all Synopsys DesignWare DDR PHYs (excluding DDR2/DDR PHYs)
  • DFI 2.1 compliant interface to DDR PHY (DFI 3.1 is backward compatible with DFI 2.1)
  • Data rates up to 2133 Mbps in 1:2 frequency ratio, using a 533 MHz controller clock and 1066 MHz memory clock (dependent on process)
  • Data rates up to 1600 Mbps in 1:1 frequency ratio, using a 800 MHz controller clock and 800 MHz memory clock (dependent on process)