The Synopsys DesignWare® Ethernet MAC 10/100/1G Universal Core enables the host to communicate data using the Gigabit Ethernet protocol (IEEE 802.3). The Ethernet MAC 10/100/1G Universal Core is composed of three main layers: The Gigabit Ethernet Media Access Controller (GMAC), the MAC Transaction Layer (MTL), and the MAC DMA Controller (MDC). The MTL is highly configurable enabling optimum performance supporting a wide range of implementations based on end-system applications. A multitude of application interfaces are supported as well for easy SoC integration. Silicon proven and designed for easy integration into ASICs and FPGAs the DesignWare 10/100/1000 Universal MAC comes with a user friendly application interface so designers can easy set their functional and implementation objectives to meet design requirements. The core is verified using state of the art methodologies to reduce risk. This includes the RTL design, verification, hardware verification and interoperability tests.
DesignWare Ethernet MAC 10/100/1000 Universal Block Diagram
 DesignWare Ethernet MAC 10/100/1000 Universal Datasheet
General Features
- Compliant with IEEE 802.3 specifications
- Support for IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization
- Supports:
- IEEE 802.3-az for Energy Efficient Ethernet (EEE)
- IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on flow control input de-assertion.
- IEEE 802.1Q VLAN tag detection for reception frames
- AMBA 2.0 for AHB Master/Slave ports and AMBA 3.0 for AXI Master/Slave ports
- Configurable to support data transfer rates of 10/100/100 Mbps, 10/100 Mbps only or 1000 Mbps only
- Multiple TCP/IP offload functions supported
PHY Interfaces
- Gigabit Media Independent Interface (GMII)
- Media Independent Interface (MII)
- Reduced GMII (RGMII)
- Serial GMII (SGMII)
- Ten Bit Interface (TBI)
- Reduced MII (RMII)
- Serial MII (SMII)
- Reduced TBI (RTBI)
- Reverse MII (RevMII)
Application Interface Features
- Fully synchronous design operating on a single system clock
- Supports:
- 32/64/128-bit data transfers
- Individual programmable burst size for Transmit and Receive DMA Engines
- Descriptor architecture allowing large blocks of data transfer with minimum CPU intervention & comprehensive status reporting for normal operation and transfers with errors
- Programmable interrupt options for different operational conditions
- Provides per-frame Transmit/Receive complete interrupt control
- Provides separate ports for host CSR and host DATA access configurable for FIFO, APB, AHB, or AXI interfaces
- Supports:
- Start and stop modes
- All AHB burst types
- AXI low-power interface
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