The DesignWare AXI DMA controller is a highly optimized centralized AXI DMA IP component offering configuration of up to 32 channels for a range of applications.
A flexible, multi-interface, centralized AXI DMA controller
(View Product Details for DW_axi_dmac):
- Independent core, slave interface, handshaking interface and master interface clocks
- Configurable for up to 32 channels, one per source and destination pair
- Configurable for up to 64 handshaking interfaces
- Data transfers in one direction only (each channel is unidirectional)
- Supports AHB and APB4 protocols for Slave interface
- AMBA 3 AXI and AMBA 4 AXI protocols for Master interface
- Support for up to 2 AXI master interfaces
- Two master interfaces for multilayer support
- Multiple AXI masters increase bus performance by allowing direct connection of peripherals on different AXI interconnects
- Support for different ACLK on different AMBA layers
- Data bus width up to 512 bits for master interface
- Programmable outstanding transaction limit per channel on the master interface
- Configurable AXI transfer width to support narrow transfer width 8, 16, 32, 64, …, 512 bits
- Out-of-order transaction support for different channels connected on same master interface
- Endian mode can be selected statically or dynamically for AXI master interfaces
- Independent control for endian scheme of linked list access on master interfaces
- AXI Unique ID support per channel to avoid the need for having re-ordering buffer at the SoC level
- Supports AXI Unaligned Transfers
- Support for Context Sensitive Low Power feature
- Programmable/configurable transfer type support for each channel (memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral)
- Programmable/configurable flow control support at DMA transfer level (DMA FC, Source FC, and Destination Flow Controller)
- Programmable multiblock transfer using Linked List, Contiguous Address, Auto Reload, and Shadow Register based
- Supports asynchronous Hardware handshake feature
- Separate external memory interface (per channel) to connect SRAM or Register File based memories to Channel FIFO
- Optional identification register
- Channel locking functionality Supports locking of the internal channel arbitration for the master bus interface at different transfer hierarchy
- DMAC status indication outputs idle/busy indication
Helps users meet design requirements for safety-critical applications:
- Lock Step Protection feature
- Channel/Unique ID Memory ECC Protection
- AXI Interface ECC protection
- AHB/APB4 Interface Parity protection
Products
Downloads and Documentation
Description: |
AMBA 3 AXI DMA Controller |
Name: |
DW_axi_dmac |
Version: |
2.00a |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Library IP |
Documentation: |
Hide Documents...
Databooks DesignWare DW_axi_dmac Databook (2.00a) ( PDF )
DesignWare DW_axi_dmac Databook with changebars (2.00a) ( PDF )
Doc Overview Guide to Documentation for DesignWare Synthesizable Components for AMBA 2 and AMBA … ( PDF )
Installation Guide DesignWare Synthesizable Components for AMBA 2, AMBA 3 AXI, and AMBA 4 AXI … ( PDF )
Release Notes DesignWare Synthesizable Components for AMBA 2, AMBA 3 AXI, AMBA 4 AXI Release … ( PDF )
User Guide DesignWare Synthesizable Components for AMBA 3 AXI and AMBA 4 AXI User Guide ( PDF )
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Toolsets: |
Qualified Toolsets |
Download: |
AXI |
Product Code: |
A415-0 |