Synopsys IP Solutions for AMBA - AXI DMA Controller

The Synopsys AXI DMA controller is a highly optimized centralized AXI DMA IP component offering configuration of up to 32 channels for a range of applications.

A flexible, multi-interface, centralized AXI DMA controller (View Product Details for DW_axi_dmac):

  • Independent core, subordinate interface, handshaking interface and manager interface clocks
  • Configurable for up to 32 channels, one per source and destination pair
  • Configurable for up to 64 handshaking interfaces
  • Data transfers in one direction only (each channel is unidirectional)
  • Supports AHB and APB4 protocols for Subordinate interface
  • AMBA 3 AXI and AMBA 4 AXI protocols for Manager interface
    • Support for up to 2 AXI manager interfaces
    • Two manager interfaces for multilayer support
    • Multiple AXI managers increase bus performance by allowing direct connection of peripherals on different AXI interconnects
    • Support for different ACLK on different AMBA layers
    • Data bus width up to 512 bits for manager interface
    • Programmable outstanding transaction limit per channel on the manager interface
    • Configurable AXI transfer width to support narrow transfer width 8, 16, 32, 64, …, 512 bits
    • Out-of-order transaction support for different channels connected on same manager interface
    • Endian mode can be selected statically or dynamically for AXI manager interfaces
    • Independent control for endian scheme of linked list access on manager interfaces
  • AXI Unique ID support per channel to avoid the need for having re-ordering buffer at the SoC level
  • Supports AXI Unaligned Transfers
  • Support for Context Sensitive Low Power feature
  • Programmable/configurable transfer type support for each channel (memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral)
  • Programmable/configurable flow control support at DMA transfer level (DMA FC, Source FC, and Destination Flow Controller)
  • Programmable multiblock transfer using Linked List, Contiguous Address, Auto Reload, and Shadow Register based
  • Supports asynchronous Hardware handshake feature
  • Separate external memory interface (per channel) to connect SRAM or Register File based memories to Channel FIFO
  • Optional identification register
  • Channel locking functionality Supports locking of the internal channel arbitration for the manager bus interface at different transfer hierarchy
  • DMAC status indication outputs idle/busy indication

Helps users meet design requirements for safety-critical applications:

  • Lock Step Protection feature
  • Channel/Unique ID Memory ECC Protection
  • AXI Interface ECC protection
  • AHB/APB4 Interface Parity protection


Downloads and Documentation
AMBA 3 AXI DMA ControllerSTARs Subscribe
Description: AMBA 3 AXI DMA Controller
Name: DW_axi_dmac
Version: 2.03a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Library IP
Toolsets: Qualified Toolsets
Download: dw_iip_DW_axi_dmac
Product Code: A415-0, E137-0, H616-0, I356-0