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Performance Analysis Using ARC EV7x Fast Performance Model

To deliver the most competitive and efficient solution for performance modeling, the designer must perform Design Space Exploration (DSE) to balance all of the available features and determine the optimal hardware configuration for the given neural network model. In addition, in certain cases, the designer needs to optimize both the neural network model and the hardware to achieve the required performance, power, and area (PPA) targets in a process known as hardware/software co-design. However, performing design space exploration using actual hardware RTL descriptions is very time consuming and expensive. To this end, this paper proposes a simulation model that allows the designer to evaluate the performance of a given DNN on the underlying hardware architecture. Such a model is able to execute the model and runtime and produce a set of key performance indicators (KPIs) that can be used to analyze the performance. Such KPIs include cycle count and latency, memory reads and writes, and final frames per second. By using simulation, the final RTL is not required. Instead, a hardware model is created that captures the key microarchitecture details in a way that enables the model to produce very good approximations of the KPIs.

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