Achieving Your Low Power Goals with Synopsys Ultra Low Leakage IO

Achieving Your Low Power Goals with Synopsys Ultra Low Leakage IO

The demand for low power design has intensified with shrinking geometries. At the same time, innovation in battery operated, handheld devices has increased the design complexity by adding more and more functionality. The focus is on power-optimized designs while maintaining low cost and reduced risk. Designers face these complex and contradictory challenges: developing products with the lowest possible power consumption, maintaining high performance, integrating new connectivity standards, and moving to the smallest process technologies while keeping costs down.

Optimizing the power helps extend battery life, one of the most critical requirements in consumer and mobile applications. General Purpose IOs (GPIOs) are an essential block in a system-on-chip (SoC). GPIOs are the standard chip interface that communicates between on-chip logic operating at low voltages and off-chip components operating at similar or higher voltages. As functionality is added to the SoC, the number of pin connections to the external interfaces increases, and therefore the number of GPIOs needed in the SoC increases. With so many GPIOs in a design, it is critical to ensure they consume as little leakage power as possible to minimize the impact on the overall leakage at the SoC level while maintaining high frequencies of 100s of MHz for proper IO operation.

Leakage is often considered a device artifact that cannot be avoided, however, experienced IP designers adopt different design techniques to reduce leakage in the IOs. One example is to use Foundry-provided Ultra Low Leakage (ULL) Metal Oxide Semiconductor (MOS) devices. Unfortunately, because these MOS devices have higher threshold voltages, which reduce the device performance and circuit performance, they are of limited use. Therefore, designing the circuits to alleviate any leakage paths in the design is critical.

This whitepaper explains the need for ULL GPIOs, the optimization techniques used to reduce leakage, and the inherent tradeoffs to consider. Finally, it describes how Synopsys ULL GPIOs help designers reduce leakage while achieving the SoC power and performance targets for mobile and battery-driven devices used in AI and sensing applications.

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