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Synopsys DesignWare SATA Device Controller IP

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Synopsys' DesignWare® IP for Serial ATA (SATA) Device Controller is compliant to the SATA specification revision 3.0 (backwards compatible to SATA 2.6) supporting 1.5, 3 and 6Gb/sec operation, ensuring scalability and reuse in current and future system-on-chip (SoC) designs. The DesignWare SATA digital device controller offers an integrated DMA with a well-defined, flexible programming model that minimizes software overhead, ensuring maximum operational performance. Sample device firmware for various applications is available, speeding system integration. The solution has passed the SATA-IO Building Block Interoperability Testing, the golden standard of compliance to the SATA Specification.

The DesignWare SATA device core IP configuration offers one-click integration with the DesignWare SATA PHY IP, removing the effort of integrating the digital and mixed-signal portions of the SATA interface design. Reduced gate count and very low power consumption is achieved by utilizing the set of highly configurable options which enable the core to be optimized based on the exact design requirements. The test environment for the DesignWare SATA digital device controller IP includes a number of the DesignWare Verification IP components offering SATA transactions generation, SATA protocol monitoring and AMBA subsystem transaction generation. Verilog-based tests are provided as examples to accelerate system integration.

You can view all Synopsys SATA videos here.

DesignWare IP for Data Centers Brochure
DesignWare SATA Complete Solution Datasheet
 



DesignWare® SATA Demonstration
See how Global Unichip (GUC) utilized Synopsys' silicon-proven DesignWare® SATA IP in its Solid State Device (SSD) GP5080 platform to demonstrate a netbook boot-up time of less than half a minute. The hardware platform consists of a high-performance 32-bit ARM7 processor, SATA 3Gb/s interface, SLC/MLC NAND Flash management of up to 4 channels, 8 banks with ECC.

Kurt Huang
Director of Marketing, Global Unichip Corp.

  • Internal DMA engine with flexible programming model
  • Included Example Command Layer firmware
  • Optional RX Buffer (elasticity buffer) for recovered clock systems
  • Optional 8B/10B encoding/decoding
  • Optional OOB detection/generation logic
  • Data scrambling
  • Speed negotiation when TX OOB signaling is enabled
  • Full Power Management Features Supported
  • Supports SATA defined BIST Modes
  • Configurable AMBA System Interface
  • Supports disabling of RX and TX clocks during power modes
  • Highly configurable PHY interface
  • Additional, user defined PHY status and control ports
  • Validated with Synopsys and third-party PHYs
  • SATA-IO Building Block Interoperability Tested
SATA Device 3Gb/s AHB InfSTARsSubscribe
SATA Device 6Gb/s AHB InfSTARsSubscribe

  Description SATA Device 3Gb/s AHB Inf
  Name dwc_sata3g_device_ahb
  Version 1.50a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download dw_iip_DWC_dsata
  Product Code 4672-0
  
  Description SATA Device 6Gb/s AHB Inf
  Name dwc_sata6g_device_ahb
  Version 1.50a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download dw_iip_DWC_dsata
  Product Code 6870-0