ARC Processor Summit Proceedings
Audio - Achieving 7X Better Power Efficiency with a Unique Sub-Threshold Technology Implementation of an ARC EM5D Processor Based Subsystem
The emerging Internet-Of-Things (IoT) market is causing the focus of IC design flows to shift from increasing performance to reducing power in order to meet the demands of battery operated devices to increase their battery lifetime. PLSense has developed comprehensive technology for sub-threshold libraries and design flows, which enables the design of ICs that can operate at voltages as low as 0.45V while significantly improving battery life compared to existing solutions. As part of this technology, PLSense implemented an MCU chip fabricated on the TSMC 40-nm ULP process using Synopsys' DesignWare® Smart Data Fusion IP Subsystem. This presentation will describe the implementation of the MCU using the sub-threshold technology and show how it achieved up to 7X better power per MHz than comparable solutions.
Uzi Zangi, CEO & Co-founder, PLSense
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