ARC Processor Summit Proceedings

Presentation - Reducing System Power, Area, and Latency Using Tightly Coupled Memories and Peripherals

The increasing demand for better filtering and processing capabilities of the processor within embedded systems is causing shift from tightly coupled 8-bit microcontrollers to bus-based 32-bit processor. As a consequence, the power, performance and area (PPA) tradeoffs have also shifted in favor of performance, at the expense of power and area. This presentation will cover how closely coupled memories and processor extensions can be leveraged to improve the power and area of these embedded systems by making the bus infrastructure superfluous. Removing the bus infrastructure reduces area costs as well as the latency when accessing memories and peripheral registers. Reduced latency translates into further performance improvement and power reduction. Improving the PPA ratio of an embedded system by tightly coupling memories and peripherals is demonstrated by comparing a bus-based implementation of a sensor hub versus a tightly coupled, bus-less implementation.
Ad Vaassen, ASIC Digital Design Engineer, Synopsys

Thank you for your interest in the presentations from the event.

Please complete the registration form and click the 'continue >>' button below.

Required Required Fields

Business Email:Required
First Name:Required
Last Name:Required
Job Title:Required
Postal/Zip Code:Required