ARC Processor Summit Proceedings

Reducing Dynamic Power and Time-to-Tapeout for High-Performance AI Processor SoCs

Developing new AI applications requires implementing cutting-edge technologies while meeting performance, power, area and time-to-market requirements. Edge applications require low power, while CNN engines can be especially challenging to a design's power budget due to the density of the multiply-accumulates needed to run large neural network computations. In addition, designers can face tedious and time-consuming iterations for floor planning and routing in order to meet PPA targets. This presentation will describe how usage of specialized logic cells and memories can address specific RTL-to-GDSII implementation challenges for CNN engines while reducing time-to-tapeout with optimal PPA. We will show a case study describing how utilizing the HPC Design Kit of logic libraries and embedded memories optimized for the DesignWare EV61 Embedded Vision Processor resulted in lower power and faster design closure.
Yudhan Rajoo, Sr. Technical Marketing Manager, Synopsys

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