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New SolvNet articles on DW IIP, VIP and DW Cores featuring AMBA, PCI Express and more

The Corporate Applications Engineering team has added a lot of new articles about Synopsys DesignWare IP, the world's most widely-used, silicon-proven IP which provides a broad portfolio of synthesizable implementation IP, hardened PHYs and verification IP for ASIC, SoC and FPGA designs.

The articles added on DesignWare building blocks and high speed datapath components will help you quickly understand how to manually pipeline DesignWare components and how to get rid of synthesis errors for DW_tap, DW_tap_uc and DW01_bsh components.

The articles added on DesignWare AMBA On-chip bus will help you in understanding about DW_ahb's remap and EBTEN feature, when and how to use it in your subsystem. Also, if you have both AHB and AXI subsystems, you can learn how to bridge both the subsystems using DesignWare Synthesizable IP.

Several new articles have also been added on the DesignWare Cores such as PCI Express. For a complete list of new articles added to the SolvNet repertoire on DesignWare Library (IIP and VIP) and DesignWare Cores,  please see below.

  1. Enhancement in DesignWare Tap Controllers DW_tap and DW_tap_uc (019003)
  2. 2004.12-SP3 to 2004.12-SP5-1 gives bad logic for DW01_bsh (019311)
  3. Pipelining DesignWare building blocks (019832)
  4. Bridging Solution Using DesignWare Synthesizable IP between AHB and AXI subsystems (019516)
  5. DW_ahb EBTEN feature (019521)
  6. How to use AMBA Memory Remap Feature in DW_ahb (019515)
  7. Synthesizing a DesignWare Core to an FPGA target (016615)
  8. Missing Interfaces in DW_memctl 2.73a or later (019500)
  9. PCI Express Core: What is the difference in BAR setup between Type1 and Type0 Configuration Space? (019214)
  10. DWC PCI Express Default Target Setting (019478)
  11. PCI Express Core: ELBI Interface Limitations (019212)
  12. RAM sizing calculation for the DWC PCI Express cores (019471)
  13. When should the application RESET the PCI Express Core? (0192107)
  14. PCI Express Core: Transmit or Client Interface TLP formation (019213)
  15. Which WakeUp or Beacon Signaling do the PCI Express Cores Support? (019211)
  16. DWC PCI Express Power Consumption (019486)
  17. DWC PCI Express Cores Error Handling (019477)
  18. Modifying Completion timrout for PCI Express Cores (019641)
  19. PCI Express Core Initialization Sequence (019210)
  20. Help getting started with the DWC PCI Express Cores  (019472)
  21. Preventing DWC PCI Express core from entering L2 state (019485)
  22. Programming UDC Registers (019701)
  23. Using other logical endpoints as a control type endpoint (019703)
  24. Closing a Descriptor Channel for a Bulk/Interrupt Out Transfer Flow for DesignWare USB 1.1 Device Subsystem-AHB/VCI (019572)
  25. Control IN (Get_Descriptor) Transfer Flow for DesignWare USB 1.1 Device Subsystem-AHB/VCI (019580)
  26. Closing a Descriptor Channel for a Bulk/Interrupt Out of Transfer Flow for DesignWare USB2.0 Device Subsystem AHB/VCI (019571)
  27. Signal Connections between DesignWare core USB 2.0 Device Subsystem-AHB/VCI and Synopsys USB 2 PHY UTMI+Level 3 (019680)
  28. Retry Response Handling for DWC PCI Express Cores (019851)
  29. What is the purpose of the CLIENT PULLBACK feature ? (019122)
  30. How to send a zero-length packet? (019676)
  31. What is the use of I2C interface (019677)
  32. DWC SATA Host – Initialization procedure (019863)
  33. DesignWare Cores Ethernet MAC 10/100/1000 Mbps Universal Core: Setting and clearing the own bit functionality in transmit and receive descriptors (019825)
  34. DWC Ether GMAC-Universal IP: Updating GMAC Configuration Register in RGMII Configuration (019407)
  35. DWC Ether GMAC-Universal 3.x IP and Auto-Negotiation Support in PCS Mode of Operation (019417)
  36. DWC Ether MAC 10/100/1000 Mbps – Universal IP 3.x – Software driver (019523)
  37. How do I set the equivalent of a VMT message watchpoint in VMM? (019435)
  38. Advanced Stimulus Generation with DesignWare Verification IP and VMM for system Verilog (019030)
  39. Accessing Slave Memory in VMM Using DesignWare AHB and AXI VIP models (019711)
  40. AHB Verification IP: Use of the “index” parameter in the get_mem_response command (019885)
  41. OCP: How do I validate my configuration? (019849)