HOME   IP   TECHNICAL BULLETIN   ARTICLE ARCHIVES   ARTICLE

DesignWare Technical Bulletin Article

Search Tools

Spotlight

Low Power Methodology Demystified: Insights into the LPMM

Synopsys and ARM introduce the Low Power Methodology Manual (LPMM) - a how-to guide for managing power in SoC designs. Phil Dworsky and Ian Thornton explain why the LPMM is a must-read for anyone designing, or getting ready to design, SoCs for low power applications.

With the explosion of the number of wireless devices, the demand for increased functionality of those devices, as well as skyrocketing energy costs, managing SoC power has become an economic imperative for the success of almost every chip company. As companies move to process technologies of 90-nm and below in pursuit of economic advantage, the design challenges are compounded. Through enhanced tools, IP and the LPMM, ARM and Synopsys aim to make what was formerly the domain of only leading edge designs and designers available to the designers of mainstream SoCs requiring aggressive power management in the current or next designs.

The manual specifically describes the low power design aspects of complex IP such as USB, PCI Express and Bus Infrastructure. The DesignWare USB On-the-Go IP is featured as an example of a core that implements low power techniques such as power gating and multi-voltage design.

Read the full article and download the free PDF electronic version of the LPMM