System-on-chip (SoC) complexity is being driven by platform convergence and the need for more processing power and lower power consumption. The complexity of SoC standards-based interfaces has similarly increased for the same reasons: low power, improved quality of service and high throughput. Design teams have adopted IP and reuse for designs of these complex protocols so they can focus their efforts on value-added parts of the design. However, verification teams still need to validate the integration and correctness, which require significant protocol expertise.
PCI Express is an excellent example of where design reuse and adoption has become the norm for design teams, so while the verification teams are no longer faced with full compliance testing they are still challenged with validating that the PCI Express (PCIe) design IP is functioning correctly in the context of the SoC. Clearly, this has a major effect on the verification effort. After all, the verification teams working on integration test shouldn't need to worry about compliance; that should have been taken care of by the IP provider's extensive verification, certification and wide usage in the industry. This whitepaper gives a few pointers on what should be included in integration test and how to get it done efficiently.
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