An increasing number of ASIC and FPGA designs are accelerating algorithms and applications directly in hardware (HW) circuits. These HW accelerator cores have become commonplace and are now a key part of product differentiation and the ability to meet market expectations in performance, cost and reliability.
However, the implementation and verification of hardware acceleration cores is very difficult, especially due to the growing complexity of standards in video, imaging, wireless, and other multimedia and communications applications. RTL methodologies for IC design and verification are struggling to address this complexity in terms of productivity, available resources and time-to-market.
Over the years, the semiconductor industry has been using C/C++ high-level synthesis (HLS) tools as one way to address these complexity problems. However, multiple challenges have limited the adoption and scalability of these tools..
Download this whitepaper to learn more about these challenges and how Synopsys Synphony C Compiler (SCC), a new high-level synthesis product from Synopsys, addresses the challenges in high-level synthesis adoption.