The MIPI DigRF interface is a high speed, serial, digital chip to chip interface and communication protocol between Baseband processor ICs and RF IC enabling increased reliability, lower power, lower pin count and increased interoperability.
The MIPI DigRF v4 specification is based on a scalable architecture. This architecture provides significantly higher bandwidth than the DigRF 3G version and relies on the MIPI M-PHY as a physical layer. It is intended to be used in mobile terminals that support high bandwidth mobile broadband technologies such as LTE and Mobile WiMax.
The DesignWare DigRF v4 Master Controller IP core implements all the functionalities defined for the protocol layer of the DigRF v4 interface. It is fully configurable to enable support for 1 TX Channel and up to 2 RX Channels and can be used for basic handset configurations as well as with local and remote diversity. DesignWare DigRF v4 Master Controller Datasheet
Demo of DesignWare MIPI DigRFv4 and M-PHY IP Demo of proven system-level interoperability using Synopsys' DesignWare MIPI DigRFv4 and MIPI M-PHY IP solutions.