Verification White Paper Download

Verdi Transaction Debug Solution: Unified Performance Analysis and Debug for Interconnect

In modern systems on chip (SoCs), where Arm® AMBA® protocols are intensively used as standard intellectual property (IP) interfaces, the interconnect is usually required to bridge and facilitate the communication between many different IP interfaces. The interconnect presents one of the biggest challenges of SoC verification, considering the different kinds of protocol interfaces, conversion of different transaction types, and the large number of masters and slaves. The verification effort becomes particularly significant when multi-layered interconnects are involved, since they are large combinational transaction paths that are very difficult to imitate using normal scoreboards or predictors. Fortunately, interconnect verification IP and validation solutions are available to bring greater efficiency and accuracy to the process. From a technology perspective, AMBA AXI (Advanced eXtensible Interface) provides the means to perform low latency, high bandwidth on chip communication between multiple masters and multiple slaves. Here the main challenge comes that how these masters are interacting with slaves, in other words which master is getting data/address exchange with which slave.

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