Design and verification reuse lies at the very heart of every modern chip development effort. A system on chip (SoC) project with billions of gates cannot possibly be completed in reasonable time without leveraging blocks from prior projects and commercial intellectual property (IP) offerings. These reused blocks are themselves challenging to develop since they are as large and complex as previous generations of chips, and they may also rely on reuse to meet demanding schedules. Although design reuse is not without its challenges, it is well understood and widely adopted. However, verification reuse is typically quite limited, especially up and down a chip hierarchy. This creates complications when debugging designs and can delay product release. This white paper discusses some of these challenges and presents the novel technique of waveform reuse in Synopsys Verdi® Automated Debug System as a way to reduce debug turnaround time (TAT) by a factor of ten and thereby shrink time to results (TTR) and time to market (TTM) for SoC designs.