Designing secure silicon requires the design to be stable at all times, it shouldn't enter unknown states at any time to make it vulnerable from the security point of view. This paper identifies different sources of instability such as combinational feedback loop, unguarded clock and reset crossing, unguarded power crossing, etc. These instabilities can lead to unknown value propagation and high electrical currents, which can cause illegal state transition and lead to a breach of security policies, where confidential data and computation are compromised. Static verification techniques can help identify design defects much earlier in the design flow and at considerably lower verification costs. Due to the emergence of a very complex reset architecture and the requirement of rapid power-down and power-up, Reset Domain Crossing (RDC) has become a new verification complexity. This paper also provides insight into RDC verification technologies that can handle today's design and reset complexities.