Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and maximizes productivity of physical design teams.
This paper presents the need for multi-level physical hierarchy floorplanning, the challenges inherent with this style when using tools limited to two levels of hierarchy, and discusses how IC Compiler II addresses these challenges.
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