Synopsys Formality White Papers

Formality® Introduces Error-ID Technology

Have you ever experienced the "now what" anxiety that accompanies a failing equivalence checking verification? Have you found yourself staring at a logic cone with thousands of gates and no clear place to start the debug process?

Synopsys is pleased to make available to its customers and prospective customers a paper that discusses new technology focused on solving this challenge, free of charge.

Please complete the following form then click 'continue >>'.

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1.	What is your current interest in Equivalence Checking?
	Current technology user Investigating for future use Just curious
2.	What is the most important aspect of an equivalence checking tool? (Check all that apply)
	Verification run time Capacity Ease of setup to ensure first-pass results Debug of real design differences Language compliance with synthesis tools Advanced arithmetic verification Retiming verification Verification of ECOs Other, please specify:
3.	Which RTL language will most likely be used on your next design?
	VHDL Verilog SystemVerilog
4.	How would you best describe your role?
	Verification Engineer Verification Engineering Manager/Lead CAD Engineer CAD Engineering Manager/Lead Design Engineer Design Engineering Manager/Lead Corporate Management (VP, President, CTO, CEO, COO) Marketing/Sales/Business Development Other
5.	Do you want to be contacted to learn more about Formality?
	Yes No

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