Optimizing DDR Memory Subsystem Efficiency Part 1 - The Unpredictable Memory Bottleneck

Optimizing DDR Memory Subsystem Efficiency
Part 1 - The Unpredictable Memory Bottleneck

The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, they provide sophisticated Quality of Service (QoS) features to satisfy the specific bandwidth and latency requirements from individual SoC components. However, a large number of design parameters and configuration registers need to be tuned for the specific application to take advantage of these advanced capabilities.

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