There is an overwhelming increase in asynchronous resets in today's system-on-chip (SoC) designs due to low power, third-party IP integration and software requirements. Asynchronous reset verification is generally overlooked in ASIC and FPGA design assuming correct by construction and verified through dynamic simulation or manual reviews. Designers can reset their logic in multiple ways, but need a thorough verification methodology to make sure that asynchronous reset domain crossings (RDC) do not introduce new bugs, which can result in silicon failures and even stop the device from booting correctly. This webinar focuses on the reset domain crossing problem, how it manifests in designs and pin points the gaps that exist in verification methodology.
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