This Synopsys webinar discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain crossing (CDC) or reset-domain crossing (RDC) paths or break the synchronization of pre-qualified CDC/RDC paths. This may result in subtle bugs to escape to silicon which traditional CDC/RDC tools cannot catch. You will learn the new approach for power aware CDC/RDC verification.
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