Verification Videos

Exhaustive Formal Verification of Packet-Based Designs

Verification of designs that transport data in a serial manner is a known challenge for both simulation and formal verification. The complexity of such designs stems from the serialized nature of packet flow, where the state of each packet depends upon the history of all the previous packets in flight. These type of designs can be seen all around in network routers, bus protocols, bus bridges, load-store units in CPU, packing and unpacking designs, and SoC peripherals such as I2C, I2S, USB, UART, and Ethernet.

This webinar presents a case study to verify a packet-based design using the Synopsys VC Formal Property Verification (FPV) app. The crux of the solution presented is based on abstraction. Based on experience and coupled with VC Formal’s ease of use, abstraction provides a powerful tractable solution to an otherwise intractable problem. In addition, the multi-property proof engine technology of the FPV app aids abstraction-based methodology and provides a significant speedup in the computing performance and tractability required to build exhaustive proofs for such packet-based designs.

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