With debug now consuming close to half the time spent in the verification cycle for a project, leveraging automation and smarter technology has become even more significant. This Synopsys webinar will discuss the elimination of two separate flows for debug and simulation leading to a single unified compile flow which ensures consistency between the simulation and debug environments. We will demonstrate some of the latest features introduced in Verdi which enable faster loading of large design databases. We will also demonstrate how reverse interactive testbench debug features like what-if analysis and constraint debug aid in greater efficiency without having to run multiple iterations of recompile and simulations. Lastly, we will review how Verdi, as a unified debug platform, supports debug across the Verification Continuum™ platform including static, formal, emulation, FPGA and coverage debug.
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