Part 1 of this Synopsys webinar series discussed how increasing SoC design complexity is leading to a huge number of clock domain crossings (CDC), making CDC verification cumbersome and time consuming. The number of CDC crossings forces the use of waivers in the final design signoff due to tight design schedules, which masks silicon bugs that are then found during tapeout. To avoid these issues, we introduced a constraint-driven CDC methodology and how it’s used to achieve a high-quality signoff. Part 1 of webinar can be watched at this link.
Part 2 of this series will detail how to apply a constraint-driven CDC methodology, what are CDC specific constraints and their semantics, and finally how a user can define and verify these constraints to address complex CDC problems. Part 2 of webinar can be watched at this link.
Part 3 of this series will talk about machine learning-based Root Cause Analysis (RCA) for CDC. Machine learning RCA automatically identifies where to define constraints, enabling high-quality CDC analysis with faster turnaround time, leading to huge productivity gains.
Please complete the following form, then click the 'continue >>' button below.