With the increasing complexity of SoC designs due to demand for higher compute power and lower power the proliferation of asynchronous clock domain is the new normal. This leads to a huge number of clock domain crossings (CDC) making CDC verification and debug cumbersome and time consuming. The high CDC crossings often promotes waivers in the final design sign-off due to schedule. The waivers leave unverified silicon bugs that lower the quality of the final product.
In part 1 of this webinar series, we will discuss how Constraint driven CDC methodology will define and verify the design intent with less chance of missing real RTL bugs. We will cover best practices and case studies on how our customers are using this methodology to solve complex CDC problems and how it has benefited them.
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