As SoC designs get more complex, they are configured with multiple modes for different applications. Traditionally, the analysis of clock domain crossing (CDC) relies on multiple sets of constraints, each defining a design mode and analyzed separately. This flow is not sustainable for large projects, for which manual specification of all the different modes to analyze is simply infeasible. In practice, designers must focus only on critical mission modes, resulting in missed bugs.
This Synopsys webinar will showcase a solution for a comprehensive multimode CDC analysis using structural and formal methods, where a single set of constraints is applied to analyze the design with significant reduction in false violations. This new approach guarantees 100% CDC coverage while saving time for the verification team to focus on real violations for CDC signoff.
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