Next-generation SoCs with advanced graphics, computing and artificial intelligence capabilities are posing unforeseen challenges in verification. Designers and verification engineers using static verification technologies for low power, clock domain crossing (CDC), and reset domain crossing (RDC) analysis often see many violations in the initial stages when the input constraints are inadequate. Efficient debugging and root-causing real issues is a big challenge when the design has a large number of violations. This webinar will talk about the current application of deterministic and machine learning-based techniques to automatically identify the accurate root-causes for a related group of violations. These techniques help to significantly reduce the overall turnaround time for verification signoff to "shift-left" and ensure that subtle bugs do not escape into silicon.
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