Energy efficient chips have become a critical need in all major markets from battery operated devices for mobile, wearables, IoT, aerospace, and automotive applications to wired applications for high performance compute (HPC), artificial intelligence (AI), datacenters, networking, and storage. This requires advanced power management through low power design techniques at early stages of design development. The power intent needed for these low power design techniques is captured through the IEEE Standard 1801 Unified Power Format (UPF). Designing this UPF file is a manual, tedious process and does not always scale from one abstraction level to another or from one tool to another in the SoC design flow. Designing and optimizing UPF needs a thorough understanding of this ever-evolving standard.