VC LP is a multi-voltage low power static rule checker that can help pipe-clean IEEE 1801 Unified Power Format (UPF) low power design intent, and validate that UPF low power design intent is accurately implemented and functions correctly. VC LP provides extensive reporting, filtering and waiving capabilities to simplify and expedite even the most complex low power verification signoff flows. VC LP provides efficient and effective low power debug capabilities. VC LP is also completely integrated with VC CDC and VC Formal. Design load and setup needs to be only done once for any or all of the three products, and all three share similar usability, reporting and debug features.