Clock domain crossings (CDCs) are a well-known source of metastability, but they are not the only source. Asynchronous reset crossings within the same clock domain can also cause metastability. The use of asynchronous resets is becoming more prevalent because of the broader use of multi-phase power-up boot sequences and increasing software asynchronous resets. Therefore, designs are now more prone to expensive Reset Domain Crossing (RDC) issues, which can add significant time and cost to design and debug cycles and may even escape in silicon resulting in expensive respins. Like CDC verification, RDC verification has become equally essential signoff criteria to ensure that the designs work per the specifications.