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VC SpyGlass Lint

Inefficiencies during RTL design development usually surface as critical design bugs during the late stages of design implementation. If detected late, these bugs often lead to a large number of iterations; if left undetected, they can lead to expensive silicon respins. The VC SpyGlass™ RTL Signoff platform, builds on the proven SpyGlass® technology for early design analysis with the most in-depth analysis at the RTL design phase. VC SpyGlass provides an integrated solution for analysis, debug, and fixing with a comprehensive set of capabilities for structural and electrical issues, all tied to the RTL description of the design.

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