Verification Datasheet Download
VC SpyGlass CDC
Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today's SoCs have dozens, sometimes even hundreds, of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify metastability effects, which lead to data transfer issues across asynchronous clock boundaries. STA tools also do not address asynchronous clock domain issues.
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