Verification Debug White Paper Download

The Next Generation of Testbench Debug Productivity

It is widely accepted that verification consumes at least sixty percent of time and resources on most semiconductor development projects. This statistic has been borne out by many industry surveys over the last twenty years. Verification technology has had to evolve to accommodate ever larger and more complex designs. Innovations such as constrained-random simulation and the Universal Verification Methodology (UVM) have greatly reduced the effort to develop the testbench, tests and metrics required for effective simulation-based verification. Many of these techniques extend to hybrid verification combining software simulation and hardware emulation. Engineers no longer have to hand-write test vectors and stare at waveforms to determine whether the tests are passing.

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