Verification Datasheet Download

SpyGlass Lint: Early Design Analysis for Logic Designers

Inefficiencies during RTL design usually surface as critical design bugs during the late stages of design implementation. If detected, these bugs will often lead to iterations, and if left undetected, they will lead to silicon respins. The SpyGlass product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.

Please complete the following form then click 'continue >>' to complete the download.   Note: By registering, you acknowledge and agree to the terms of the Synopsys Privacy Policy.