Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery and use their best judgment and years of experience to determine when to tape out. New tools or technologies that can accelerate coverage convergence, expose bugs early in the design cycle, reduce debug effort and improve verification turnaround time have high value by 'shifting left' the verification process resulting in faster tape out and earlier software development using fewer resources.
This white paper describes an intelligent approach to coverage optimization that maximizes project resource utilization while reducing the verification schedule. It leverages artificial intelligence (AI) and machine learning (ML) technologies in the industry-leading Synopsys VCS simulator, to improve optimization over time through continuous feedback as more project experience is accumulated.