Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery, consider anecdotal information on the types of bugs that escaped to silicon in previous projects, and use their best judgment based on their years of experience to determine when to tape out. Above all, they look at various coverage metrics. Verification engineers want to see these metrics reach the target goals, or at least asymptotically converge toward these goals. Thus, any new tools or technologies that can accelerate coverage convergence, expose bugs early in the design cycle, reduce debug effort and improve verification turnaround time have high value by “shifting left” the verification process and therefore accelerate tape out and software development using fewer resources.