Functional Verification Datasheet Download

VC Verification IP for GDDR6 (Early Access)

Synopsys® VC Verification IP for JEDEC GDDR6 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of GDDR6 based designs. The VC VIP is based on next generation architecture and implemented in native SystemVerilog/UVM. VIP is natively integrated with Verdi Protocol and Memory Analyzer for easy and fast debug and Verdi Performance Analyzer to find and fix performance bottle necks.

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