Functional verification of system-on-chip (SoC) designs requires best-in-class tools linked together in a unified solution in order to address exponential complexity challenges. There is no one-size-fits-all method for verification. Complex designs require a combination of virtual prototyping, static checks, formal analysis, simulation, emulation and FPGA prototyping. The execution of all the tools in the solution must be managed to minimize project time, engineering effort and compute resources. Metrics must be gathered and aggregated in a unified way to assess verification status and determine when to tape out.