A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff.
In this whitepaper, we will describe major advances in timing signoff technologies that address the new challenges. We will cover new techniques to optimize timing accuracy and alleviate performance and capacity bottlenecks to significantly improve productivity of timing signoff, including ECO.
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