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About Platform Architect for Multi-Die Systems
Synopsys Platform Architect for Multi-Die Systems is a SystemC™ standards-based performance and power analysis tool for early architecture exploration and design of multi-die systems. It accounts for the interdependencies between multiple dies (also referred to as chiplets) within multi-die systems.
Platform Architect for Multi-Die Systems helps optimize hardware-software partitioning, IP selection and configuration, interconnect and memory configuration, and power under consideration of the die-to-die interfaces. Universal Chiplet Interconnect Express™ (UCIe™) is a library component allowing our customers build a multi-die system model.
Platform Architect for Multi-Die Systems is part of the comprehensive Synopsys Multi-Die System Solution for accelerated heterogeneous integration. The solution, including EDA and IP products, enables early architecture exploration, rapid software development and system validation, efficient die/package co-design, robust and secure die-to-die connectivity, and enhanced manufacturing and reliability.
Key Benefits
Multi-die Support
Accounts for the Interdependencies Between Multiple Dies within Multi-die Systems
Power Optimization
SoC Interconnect and Memory Subsystem Performance and Power Optimization
Partitioning & Optimization
Hardware-Software Partitioning and Optimization of Multicore Systems
Efficient Exploration
Using Traffic Generation & Cycle-Accurate TLM Interconnect Models
Features
- Support for multi-die system architectures with UCIe interconnectivity
- Largest library of architecture models
- Fastest capture of task and trace-based SW workloads
- Application specific support (AI, automotive, networking, , others)
- System-level power analysis based on IEEE-1801 UPF power monitors
- Intuitive analysis of tradeoffs and KPIs
- Fast design space sweeping and sensitivity analysis
Resources
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