Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
The lead article examines full process flows that include lithography and topography simulations. There is an introduction to Fammos for interconnect stress and reliability analysis, as well as articles describing the design and optimization of double-halo 45-nm CMOS technology, the simulation of nanocrystal nonvolatile flash memory, and the enhancements to Raphael™ in Version Z-2006.12.
Required Fields
